In the field of semiconductor memories, a non-volatile differential memory cell can be constructed from two variable threshold MNOS FETs (metal nitride oxide semiconductor field effect transistor) appropriately configured with associated circuitry, and a plurality of these cells can be fabricated as an integrated circuit to form a memory array. The positive and negative changes which can be induced in the threshold voltage of the MNOS FETs by applying a relatively high electric field across the gate insulator produces a hysteresis effect. This hysteresis effect enables use of the variable threshold MNOS FET for binary memory storage, wherein the binary states are defined by the high and low conductive threshold levels and where the memory retention time is defined as the period between the instant of writing an MNOS memory FET into a given high or low conduction threshold level and the instant when the high and low conduction thresholds become indistinguishable from each other. Subsequent to writing an MNOS memory FET into a high or low conduction threshold level, the preset level decays to a value intermediate the high and low threshold levels. The threshold levels vary from device to device and chip to chip however, and the rapidity of the decay is dependent on the write cycle level and duration, the number of read cycles and the amount of read disturb, see pending U.S. patent application of Robert J. Lodi, Ser. No. 736,651.
Valid retention beyond 10.sup.8 seconds is possible before the high and low conduction thresholds become indistinguishable, but because of the variation in threshold levels within a cell, from cell to cell and from array to array; and because retention depends on the separation of the threshold levels, it is desirable to be able to test each MNOS memory FET for its characteristic threshold levels to determine the voltage separation between the thesholds of each MNOS memory FET of a cell at any given time after writing. In this manner the memory retention characteristics of each cell of an array can be determined.
A test circuit which can individually access each MNOS memory FET in each cell of an array makes it possible to determine the composite retention characteristics of the array as well as the worst case cell of the array.